1. Field of the Invention
The invention relates to a metal-oxide-semiconductor (MOS) transistor device and a layout pattern for the MOS transistor device, and more particularly, to a lateral double-diffused MOS (hereinafter abbreviated as LDMOS) transistor device and a layout pattern for the LDMOS transistor device.
2. Description of the Prior Art
Double-diffused MOS (DMOS) transistor devices have drawn much attention in power devices having high voltage capability. The conventional DMOS transistor devices are categorized into vertical double-diffused MOS (VDMOS) transistor device and lateral double-diffused MOS (LDMOS) transistor device. Having advantages of higher operational bandwidth, higher operational efficiency, and convenience to be integrated with other integrated circuit due to its planar structure, LDMOS transistor devices are prevalently used in high operational voltage environment such as CPU power supply, power management system, AC/DC converter, and high-power or high frequency (HF) band power amplifier. The essential feature of LDMOS transistor device is a lateral-diffused drift region with low dopant concentration and large area. The drift region is used to alleviate the high voltage between the drain and the source, therefore the LDMOS transistor device can have high breakdown voltage (BVD).
It is well-known that characteristics of low ON-resistance (hereinafter abbreviated as RON) and high breakdown voltage are always required to the HV MOS transistor device. However, breakdown voltage and RON are conflicting parameters with a trade-off relationship. Therefore, a LDMOS transistor device that is able to realize high breakdown voltage and low RON is still in need.